Summary




A computer architect with 10+ years of development and design experience at top-tier organizations in academia and industry in electrical and computer engineering. Extensive programming experience in C/C++ and Perl plus experience in Java, concurrent programming in VHDL, R, Python, TCP sockets for IPC and Unix shell scripting. Experience with event-driven and cycle-based simulation and hardware-software co-simulation. Postdoctoral level research experience in improving performance and parallelism for high performance computer architectures that derived unique insights into performance modeling, analysis and optimization. Industry experience in various phases of large scale system development, architecture specification, design and coding, debugging, development of unit and system level testplans, functional and performance verification plus result analysis and production testing and performance tuning. Strong analytical and reasoning skills. Ability to solve problems independently and work with others synergistically. Equity, options and forex retail proprietary trading experience. Passionate interest in financial market trading.
SELF EMPLOYED 2009
Trading System Research and Development
Developing infrastructure for creating and evaluating algorithms for real-time tick data based systematic trading using Interactive Brokers API, multithreaded C++, TCP sockets and shared memory for IPC and R.



Employment

2005 -  2008
Computer Architect

Co-developed architecture, microarchitecture and firmware interface specifications for memory controller in a digital media system-on-a-chip processor. Drove convergence on features and design details by working with a team of hardware and software architects and designers. Developed simulation models for optimizing certain key design parameters which provided counter intuitive insights.

Devised performance evaluation strategy and testplans for units in a system-on-a-chip mobile media processor design that minimized infrastructure development. Verified performance for memory controller in a mobile graphics processor design and presented results in an insightful manner that revealed performance bottlenecks and some tricky-to-uncover bugs. Completed corporate intensive training in C++ and STL.

2003 -  2005
Postdoctoral Research Fellow

Investigated microarchitecture performance and complexity tradeoffs by modeling in a C/C++ processor microarchitecture simulator that shed new light into bottlenecks that impede performance and dissipate energy. Modeled and analyzed performance constraints on a dependence graph which is a novel approach to quantitative performance analysis and developed a dependence graph visualization tool in Java.
Proposed and evaluated algorithmic techniques for improving throughput performance in simultaneous multithreaded processors by identifying and prioritizing performance critical instructions stretching the limits of dependence graph based performance modeling approach. Performed extensive experimental evaluations by modeling in a simultaneous multithreaded processor microarchitecture simulator in C++.

1999 -  2003
Graduate Research Assistant and Graduate Teaching Assistant

Proposed the use of computation histories for improving control flow and data flow predictability and instruction level parallelism in high-performance speculative microarchitectures. Developed several hardware algorithmic techniques to derive computation history and make predictions. Published and presented this research at highly selective conferences and reviewed related work for peers. Initiated and led a multi-year collaboration with the esteemed Intel Microarchitecture Research Labs. Extensive experience with C programming for large dataset simulations using Spec2000 benchmark suite.

Teaching assistant for graduate computer architecture and undergraduate circuit and digital design courses.

2000 -  2001
Graduate Intern

Co-invented US patent # 7143272, Using computation histories to make predictions. Persuaded Intel Research Labs to grant $25000 to continue this research at the University of Maryland. Proposed, modeled and evaluated computation history based prediction techniques using a processor simulator in C.
Graduate Intern at Server Architecture Research Labs Summer 2000
Developed techniques to scale system complexity and characterized a full multiprocessor system simulation suite. Experimental framework used OLTP testcases on a simulated Windows NT multiprocessor platform.

1997 -  1999
Hardware Design Engineer

Education

Publications

1. R. Thomas , M. Franklin , C. Wilkerson and J. Stark . Improving Branch Prediction By Dynamic Dataflow-based Identification of Correlated Branches from a Large Global History , Proc . International Symposium on Computer Architecture ISCA , 2003 .
2. M. Zahran , M. Franklin and R. Thomas . Confidence Estimation for Register Value Communication in Speculative Multithreaded Architectures , First Workshop on Value Prediction VPW1 conducted along with International Symposium on Computer Architecture ISCA , 2003 .
3. R. Thomas and M. Franklin . Using Dataflow Based Context for Accurate Branch Prediction , Proc . International Conference on High Performance Computing HiPC , 2002 .
4. R. Thomas and M. Franklin . Characterization of Data Value Unpredictability to Improve Predictability , IEEE Workshop on Workload Characterization conducted with International Symposium on Microarchitecture MICRO , 2001 .
5. R. Thomas and M. Franklin . Using Dataflow Based Context for Accurate Value Prediction , Proc . International Conference on Parallel Architectures and Compilation Techniques PACT , 2001 .
6. R. Thomas et al . IEEE-1394 Technology , Open HCI Implementation and Multimedia Applications , Proc . Symposium on Computer Networking and Multimedia Systems conducted by IEEE Bangalore , India Chapter , October 1998 .
7. R. Thomas et al . Auto-Interpretation of Certain CT Scans , Proc . National Conference on Advances in Bio-medical Engineering , India , September 1997 .



Miscellaneous

Co-developed microarchitecture specifications, designed in VHDL and verified in C/C++ an IEEE-1394 link controller chip with OHCI compliant firmware interface winning Best Team Award. Recognized for extraordinary performance with IBM Special Contribution Award.
Developed an integrated VHDL/C hardware-software co-simulator/debugger for an embedded microcontroller based on customer wish list for features. Used shared memory and TCP sockets-based IPC.
OTHER RELEVANT EXPERIENCE 1997
Proposed and implemented a Haar wavelet based image classification algorithm in C for automating interpretation of CT scans that successfully detected tissue texture changes invisible to the naked eye.