Summary

US Status : Immigrant like US Green Card Holder
Nationality : Canadian

US Address : -
10368 West Rosewood Drive
Avondale, AZ 85323

Canada s Address : -
2226 Whistling Springs Crescent
Oakville, Ontario, L6M5G5

Career Objective : Seeking a challenging position in the field of CMOS/BiCMOS analog and mixed signal IC Design and RFIC Design in a progressive company offering good opportunities for professional development.

Career Profile : Architect, designed, modelled, tested and implemented mixed signal or high-speed integrated circuit products from concept to manufacture. Provided industry leading solutions for ultra low jitter clock generators/jitter cleaner PLL, CDR and SerDes.

Demonstrated experience in low voltage mixed signal IC design from concept to manufacture, verification, conformance testing and evaluate to specification in the engineering lab.

In-depth knowledge and experience in chip and block level architectures and design of Phase lock loop like PLL, fractional N PLL, Clock Data Recovery Circuits/SERDES, High Speed I/O LVDS, PECL, ECL, CML, ESD protection circuits and PLL Building Blocks : low phase noise VCO, charge pump, phase detector, phase frequency detector, dividers and input and output buffers.
Intimately familiar with submicron like 100nm IC design techniques for reducing jitter, power consumption multi Vt and multi supply trade off and reliability issues, NBTI and HCI.
Familiar with design techniques and trade-offs on reducing jitter and increasing operating frequency
Developed a mixed signal full chip level verification flow using AMS + Ultrasim in collaboration with Cadence.

Demonstrated experience in generating PLL/CDR behaviour models, top-level PLL jitter modeling and loop filter optimization, package solution, BGA/Flip chip substrate design.

experience in generating chip and block specification, jitter budget analysis, layout floor planning, placement of I/Os, differential and ended block partitioning.

experience in power estimation, checks, block reviews and documentation and applying best practices to minimize power supply noise, substrate noise, EMI and ESD issues.
Designed integrated circuits to meet the DFT and DFM requirements of the foundries CMOS like UMC and TSMC, SiGe BiCMOS like IBM 5HP/5DM/7HP and TRW InP.
Good technical knowledge of OC48, OC 192 OC 768 SONET Communication
Standards : Telcordia GR-253 CORE for SONET Transport System and Network synchronization.

Designed, build and characterized RF Receivers experience in assessment of product feasibility, schedule, costs, meeting yield targets, DFT and DFM requirements experience in testing and characterizing of high-speed

ICs Experience in developing customer reference designs and resolving customer issues.

Strong team participation skills, desire to learn, maintain design and technology awareness.
Commitment to meet deadlines.

Education and Professional Development : PhD, Department of Electronic and Electrical Engineering, University of Leeds, UK. 1995.
Masters like M. Technology in Microwave Electronics Engineering, University of Delhi, India. 1987.
Masters like MSc in Physics with Electronics Specialization, University of Delhi, India. 1985.
BSc like Honours, University of Delhi, India. 1983.

Additional Courses : Low Power Design, 2007.
RF and High Speed Design for sub micron technologies, 2007.
A course on Project Leadership and Project Management, 2003.
A course on Cadence Advanced Package Engineer 14.2 2003.
A course on Clock and Data Recovery, 2001.
A course on Liner Electronics for Fiber Systems, 2001.
A course on Microwave and Millimeterwave Engineering, 1994.
A course on Compound Semiconductor Device Modelling, 1994.

Design Skills :
Hands on experience of Cadence Design Environment includes Analog Artist, Schematic Composer, Hierarchy
Editor, AMS and Ultrasim.

experience in spectre RF, Pnoise and jitter simulations.

Hands on experience of Agilent ADS and Libra Series IV and ICCAP.

Specialized training in Cadence-Advance Package Engineer like APE simulator Strong programming experience in C/C++, MATLAB, Ocean Script, HP-VEE and BASIC.

Working experience of Linux, SUN Solaris and Hp-Unix environment.

Career Details :


Employment

2004 -  Present
Lead/Project Lead

Gennum Corp, GTA, Ontario Technical lead for the mixed-signal video timing generators that is used for clock synthesis.
Designing VCO and Charge Pump for 3Gb/s Serializer/Deserializer like SerDes and verification of SerDes.
Defined architect for a mixed signal video timing product, block partitioning, specification generation, block design, power and noise design trade-offs implementation, complete engineering responsibility to ensure functionality, testability, yield etc.
Jointly responsible for specification and characterization, liasing with appropriate team members.

Developed mixed signal test benches for verification of the PLL building blocks, top level simulation and PLL loop dynamic simulation to meet a first time right product objective.
Worked with cadence to generate a design flow for mixed signal verification using AMS and Ultrasim.

Provided technical experience in identifying, isolating and resolving customer issues with old products.

2001 -  2004
Lead/Project Leader

Technical lead for mixed-signal products : OC192/OC48/OC12 SONET like synchronous optical network clock multipliers, chip architect, a low phase noise/jitter VCO design and high speed buffer I/O.

Provided package solution and PCB based evaluation boards design and customer reference designs.
Developed verification test benches for running spice simulation which resulted in a first time right product.

Provided technical experience for bench and production test methods, high speed tests.
Provided interface of project with internal and external groups.

2000 -  2001
Senior Hardware R and D Engineer

1999 -  2000
MMIC Modeling Specialist

Design and Verification of high-speed CDR building blocks and developed characterization/measurement systems for all high-speed testing, clock and data recovery like CDR, voltage-controlled oscillators like VCOs, serializer/de-serializer like SERDES.
Worked on yield improvement and failure analysis and provided production support.
Worked on implementation of advanced device models for circuit design.

1999 -  1999
NSERC Fellow

Developed a phase lock loop module using a wideband phase frequency detector.
Worked on design of a 183 GHz PLL based receiver for phase monitoring with 8 GHz IF channel split into 3 channels 1 - 1.4 GHz, 3.7 - 4.7 GHz, and 7.3 - 8.3 GHz.

1998 -  1999
AIST Fellow

Developed a broadband like 4 GHz to 40 GHz attenuation measurement system..
Developed 3 novel fiber-optic attenuation measurement systems based on a RF substitution method, laser diode linearity and double square law detection in a subcarrier lightwave system.

1992 -  1995

Developed a physical pHEMT simulator for device and circuit characterization.
Developed a large-signal simulator for integrated power amplifier design.
Developed a small-signal modeling technique based on a novel multi-signal excitation scheme.

1995 -  1998
Scientist

1990 -  1992
Scientist

Designed and developed RF heterodyne receiver systems for precision calibration techniques.
Analysis and design of microstrip integrated circuit and antenna design.
Established automatic RF and millimetre wave measurement techniques.

Miscellaneous

Gennum s Quarterly Excellence Award.

Zarlink Semiconductor s Time-To-Market Awards for high speed SONET timing products.
Invited Researcher under Japanese Government Foreign Researcher Invitation Program.

Young Scientist Award of International Union of Radio Science like URSI in the year 1990.
Commonwealth Fellowship tenable at University of Leeds from 1992 - 1995.
Selected in Young Scientist Programme of CPEM-90, Canada and CPEM-96, Germany.
Certificate of Merit of University of Delhi for first position in the University during M. Technology

Science Meritorious Award of University of Delhi in the year 1985.

Patent
Ranjit Singh, Youcef Fouzar, Simon J. Skierszkan and Hazem A. Maguid, Capture Range Control Mechanism for Voltage Controlled Oscillators, April 30, 2003. US Pat. No : 20040217820