Objective
Seeking a full time position as a Hardware Design Engineer.

Employment

July, 2006 -  March, 2009
Application Engineer

Developed test plans and debugged printed circuit board test procedures. Worked on quotes for new PCB test procedures and generated DFT Design for Test reports to provide maximum test coverage. Interacted with customers and assisted with test procedure development. Created SRAM, SDRAM and NOR flash models and maintained application notes. Programmed Xilinx and Altera CPLDs using serial vector format files, performed BSDL file syntax verification. Familiar with board level schematics and various netlist formats. Developed scripts in a C based script language for tasks like, programming a NOR flash, driving a pattern on LEDs. Performed live customer target debug for SDRAM memory and NOR flash test issues, rendered board rework when necessary. Familiar with I2C bus protocol and assisted customers with technical inquiries on bus analysis software. Interfaced with software and hardware group to resolve technical issues, reported bugs in bug tracking system and provided timely updates to customers.

July, 2007 -  October, 2007
Engineering Intern

Worked at the Fiber in Local Loop FILL Lab as a hardware design engineer. Worked on developing a DSP based on the Haar transform to reduce/filter noise in the output signal coming from an ADC. Developed the design module in Verilog and integrated it to a VHDL master module. Performed simulations in Modelsim and Xilinx ISE. Sythesized design, checked for timing issues and downloaded Xilinx output file to the target board using the Xilinx Impact tool.

June, 2004 -  August, 2004
Teaching Assistant

Taught a robotics course at the Verizon Wireless funded Young Scholars program. Built and programmed Maze Runner and Line follower robots. The robot consisted of a microcontroller, external RAM, motors, light and touch sensors. Conducted timed robot race competitions on custom made Maze and Lines course.

March, 2005 -  May, 2006
Graduate Lab Assistant

Duties involved maintaining computer lab machines up to date with the latest software and hardware. Managed group-policy configuration for lab machines using gpedit. msc program. Imaged and ghosted XP machines using Symantec ghost host/client program. Installed and maintained various EDA programs like Verilog simulators, CAD layout tools on lab machines.

Education

Course Work
Digital Logic Design using Verilog , Digital Integrated Circuits , Advanced Microprocessor Systems , Introduction to Computer Architecture , VLSI Design and Testing , Digital Communication , Digital Signal Processing , Engineering Analysis and Introduction to Control Systems .

Projects
Datapath and Control of a Single Cycle MIPS Processor .
Designed Datapath and control for a single cycle MIPS processor in Verilog HDL .
Designed Verilog modules for ALU , instruction memory , register file , multiplexers and shifters .
Simulated waveforms in Silos Simucad simulator .
Developed test bench module to verify processor operation .
Design of a 6 Bit Digital Combinational Lock .
Designed a circuit which looks for a specific pattern of 6 - bit data in a stream of 2 - bit data in Verilog HDL .
Designed Mealy and Moore State Machines . Drew State Transition Graphs .
Optimized top level design equations using Karnaugh Maps . Designed Algorithmic State Machine Datapath charts from state transition graphs .
Design of a Parameterized Shift Register .
Designed Verilog modules for shifter datapath and control . Designed a finite state machine that controlled the parameterized shifter . States encoded using the One-Hot Coding Scheme .
Design of a BCD to Excess-3 Code Converter .
Designed Mealy and Moore State Machines , drew State Transition Graphs .
Optimized top level design equations using Karnaugh Maps .
Created a Verilog module based on Karnaugh outputs , wrote test benches to verify design functionally .
Design of a control unit for an Electronic Baseball scorecard .
Designed a control unit which keeps counts the runs scored , the number of strikes and the number of outs .
Designed 2 3 - bit up-counters which are controlled by a state machine and combinational logic .
Created standard cells like NAND and NOR from CMOS transistors and developed a custom cell library . Reused library cells to form components like D-flip-flops and counters .
Generated circuit schematics and custom layouts using Tanner schematic CAD tool .
Followed the bottom-up design approach .

Skills
Languages : Verilog HDL, VHDL, C, Perl. FPGA tools : Xilinx Synthesis ISE 6.1 webpack, Altera Quartus-2. ASIC tools : Tanner Layout L-Edit and Schematic Editor T-Spice, Orcad Pspice. JTAG tools : Corelis ScanExpress boundary scan tools, National Instruments LabVIEW. Simulation tools : Simucad Silos, ModelSim, Matlab. Lab tools : Proficient with Oscilloscope, Logic Analyzer and Digital Multimeter.


Miscellaneous
University of Madras, India, May 2003
Bachelor of Engineering in Electronics and Communication