Summary
I am looking for a job as a development Engineer.
I is a useful Engineer to get the job done.
Thanks in advance
Respectfully yours
Manish Mahajan
Manish Mahajan
Senior ASIC Design Verification Engineer
Contact Details : E-mails : ,
Phone number 1 -

15+ years of experience in Digital design for FPGA/ASIC for products based on PCI-E/PCI, SAS-SATA, Gigabit MAC Ethernet, DRAM Controller and DRAM PHY s using VHDL, Verilog and SystemVerilog verification. Hands on experience of taking high speed networking ASICs from design, architecture, verification and synthesis to tape out, ASIC testing and developing diagnostics for the chip modules, RTL design and verification, customizable product creation for different needs or customers.

Employment

November, 2005 -  Present
Senior Engineer

Work on DDR2 controller for high speed low latency data access
Worked on high speed low latency ddr2 memory controller, setup test-bench environment which was partly in perl and partly in verilog, add more tests to increase the coverage of the verilog RTL code, fixing up the environment and development of a DDR1/DDR2/DDR3/lpddr1/MobileSDRAM model based on Jedec specification, verification of the ECC bits and written a code to generate ECC code, memory controller integrated environment in vera and SystemVerilog, added test cases and ran regressions, I2C interface development and verification which was working in the labs at full speed and able to generate traffic to the main RTL core, systemverilog checker to check the data coherency for all kinds of configurations supported by the RTL. Developed a perl program to run regressions and generate coverage report for Synopsys VCS/Cadence Ncverilog/Mentor Graphics Questa simulators and a post processing perl script to go through the log files and generate a report.

December,  -  Present
Senior ASIC Design Engineer

Architect an iSCSI product and do verification of the iFCP product at the chip level. Worked on the TCP/IP hardware accelerator using the RISC processor designed to do fast network protocol processing, for the TCP and IP layers over Gigabit Ethernet MAC hardware link layer. Architect and design the iSCSI ASIC with PCI-X interface for the host with Gigabit MAC interface to the internet. Go through the iSCSI draft extensively for debug and test case development for SAN Storage/System Area Networking based ASICs.
IPSEC development and validation against C-models. SHA1/DES-3DES-CBC-ECB AES 128/256
Secure Hash Authentication code with HMAC in hardware and verify it against standard Direct C models. Developed the AES-128/256 algorithm in Verilog and verified it against the standard encryption decryption data. Develop complex mathematical models for doing GF multiplication and division.
CRC, ECC and SECDED Code

Worked on developing verilog modules for CRC and ECC SECDED which are used to detect errors and correct errors, ecc is used to correct 1 bit error and verified it against the standard c-models. Work on conceptualization of separable CRC calculation from the fragments that are received out of order and discovering a methodology of calculating separable CRC from partial segments of the packets.
I2C master design development and validation
Develop the eeprom controller for interfacing with i2c type standard interface to Atmel eeprom. Developed the rtl code for the EEPROM and verified it at block level with a made only for EEPROM I2C controller, wrote test cases so that we can verify the eeprom i2c rtl on chip level environment.
Validation of a complex blocks for Host Interface with the SAS/SATA Controller
Validate the complex communication block for interface of hardware chip with the adaptec driver interface. It involves DMA s to and Host and local memory, code download for sequencers which are built inside the chip and the IOP code download to the local memory used for IOP boot up. The validation was done using the Vera language. Did verification in Vera for XOR block which is used to perform RAID-5 redundancy in a array of disks upto 16 sources supported.
Diagnostics development for a block in the iSCSI chipset.
Developed some RISC programs for the sequencer to do diagnostic check ups for the particular blocks in the iSCSI chipset.

August, 1999 -  Present
Team Lead

Architect and define the Fibre Channel product
Architect the Fibre Channel part ; describe the hardware involved for the operation of the various protocols on the Fibre optical/electrical physical link. Lay the plan for verification of the chip. Define how the hardware takes care of the various levels in the Data Link layer.
Defining architecture for SCSI RAID system with SCSI Ultra3 dual channel
Define the next generation RAID system. Purchase and install various verification products. Develop and maintained the IP knowledge for the RAID system and SCSI ultra 3.

August, 1997 -  Present
Senior ASIC Design Engineer

Design and verify the SCSI ultra 2 or ultra 3 part
This design was done top down from scratch. Define the architecture and write the specification for implementation, diagnostics and firmware implementation. Define the mnemonics and operation code for the RISC sequencer for firmware implementation. Design bottoms up from scratch, define the architecture and write the specification for implementation, diagnostics and firmware implementation. Define the mnemonics and operation code for the RISC sequencer for firmware implementation.

February, 1996 -  Present
Design Engineer

Develop the PCI-to-PCI Bus Bridge between PowerPC and Pentium using EDA Tools. Target the design into multiple FPGA. Implement the logic that communicates between the PC side PCI with the MAC side PCI, on multiple FPGA using the PCI macro on either side. The design along with the PCI macros was laid out on 2 Xilinx 4013 devices. Test of the design on multiple FPGA. Worked on inseting testability for 0.25 micron standard cell technology ASIC.
DRAM controller for Intel Processor :
Design FPGA-based DRAM-Controller for the Intel 486 Processor. Target the design on FPGA using EDA tools. Build the design to support 32MB/16MB of memory DRAM which is used by the i486 processor. Write the verification test cases test the DRAM Controller FPGA. Optimize the design for timing violations. Inset testability for standard cell technology.

May, 1994 -  Present
Technical Staff

Education

Skills
Design Tools : front end or back end EDA TOOLS for FPGAs and ASICs Synopsys Tools : VCS/VERA, Synthesis design complier, formality fm, prime time pt Cadence Tools : NCverilog for simulations Mentor Tools : vsim and vcom on questa and modelsim FrameMaker, MS Word/PowerPoint Documentation tools Languages : VHDL/VERILOG PLI/ Direct-C of VCS/Vera Shell scripts, C and Perl


Miscellaneous
Convert serial date to parallel data and vice-versa. Target the design to FPGA and test the functionality of the serial link DS-LINK block and parallel bus PCI-BUS. Insert DFT to convert the design into ASIC.