Technically advanced Senior ASIC Design Engineer with notable professional career leading broad range of project development initiatives to design, implement and support specialized storage controller ASIC chips / circuits. Goal-oriented system engineering leader; capable of leading validation testing, coding, and integration processes to support chip development. Demonstrated expertise with VHDL/RTL/C++ system simulation tools, testbench development, and conceptual / layout design. Leadership in researching/resolving ever present evolving ASIC / SOC development issues – technically challenging projects. Interested in advancing FPGA and ASIC integration issues.
Spearheaded development and implementation of Agere/LSI DSP Core processor and assembler based tests to examine memory map logic , cache and interface applications .
Created ARM processor power-on-reset bootup code set and developed VHDL ARM bus interface state flows as a team effort to transition from TI C2XLP to ARM processor core in our disk drive controller followed by Agere processor team migration to the Marvell ARM processor POR bootup implementation .
Created new hardware or firmware simulation process using embedded test code in ASIC or SOC design , lab test bench and testing procedures .
Designed interrupt digital control logic to facilitate firmware handshake with chip core and ASIC control logic to fence out SDRAM/DDR pads during In-Circuit-Tests on drive boards .
Initiated redesign of ATA UDMA tests , in collaboration with ASIC developers , to increase test coverage at vendor chip fabrication facility . Coordinated integration of firmware code into bootrom or flash or sdram memory for ASIC/VLSI chip simulations and lab verification .
Implemented Read Channel model initialization sequence for disk sector , data transfer and Spiral Self Servo writes or reads . Drove/coordinated a low-cost method in using Analog-HDL code to implement modeling of 3 - phase , brushless stepper motors with 2 other senior engineers in collaboration with CU Boulder Engineering Department .
Enhanced In-Circuit-Test (ICT) group capabilities, creating specialized software tests to retrieve chip data from pin tester tests, redesigning chip interface control logic which minimized number of test vectors to test chips at the pad interface level, shortening test times.
Lead groups, providing the mentoring and guidance in implementing major hardware development projects for major computer disk manufacturer. Sought after for high-level technical expertise, with comprehensive knowledge of legacy and new hardware technologies. Significant contributor in major hardware engineering projects and programs, quickly gaining expertise on technology.
August, 2006 - Present
November, 1997 - November, 2006 Senior ASIC Design Verification Engineer
November, 1996 - August, 1997 Senior Engineer (Contract Employee)
Managed development of design validation tests for PCI bus – Pentium (P6) front-side bus data mover hardware and software and ASIC chipset. Developed AIX UNIX workstation tests, using Intel-based HDL code, vector coverage software, pre-written C/C++ code test functions and Intel-based backplane simulator, including C++ code conversion.
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• ASIC / SOC Development & Design Implementation• Experienced Project Lead/System Engineering• Verilog, VDHL, Perl & RTL Coding with some C++• ASIC / SOC Conceptual & Layout Design• Strategic Testbench Development • Hardware/Firmware Integration.• ASIC Validation / Verification Testing• Specialized Staff Training• Coalition Building• Collaborated VLSI implementation strategies with chip fab vendors
HARWARE EXPERIENCE
• ASIC Designs (including ECC, Memory Interfaces, RAM Design)• TI processor core to Agere/LSI DSP core to Marvell’s ARM processor POR Disk bootup transition/integration • Intel Front-Side Bus • ASIC/VHDL Cell Design and Modeling• Flip-Flop Meta-Stability Design Analysis• Read Channel Startup Sequence• ASIC Validation (including Cache, Hardware Memory Maps, Parallel ATA Interface)• Serial Test Controller ASIC Interfaces and Host Disk Controller Data Path Interfaces • Clock Generator, SOC Clock Timing and IDDQ analysis• I/O interfaces and memory/system controller interfaces SCSI chip• VHDL/SOC Disk Drive Boot-Up Sequence• SOC/ASIC Pad Design Logic implementations to support In-Circuit Test requirements• TI C2XLP DSP processor embedded code bootup simulations