Objective



To obtain a full-time position in the field of low power, process variation tolerant VLSI digital circuit and system design logic and memory that utilizes my engineering skills, analytical skills and provides me opportunities for personal and professional growth in a dynamic environment.


Summary


URL : httpwebicspurdueeduli147


Employment

2008 -  2009

The Dean's and Semester Honors for outstanding scholastics performance Graduate School Fellowship, Purdue University, summer, 2007.

2005 -  2006

Meissner Fellowship Award, Electrical and Computer Engineering department, Purdue University, 2004 - 05.

2003 -  2004

2001 -  2003

2000 -  2001

Merit Scholarship for standing 1st in Dept of Electrical Engineering, Electric Power College, Shanghai, China, 2000 - 01.

Embedded DRAM eDRAM circuit design group summer, 2008
IBM Semiconductor Research and Development Center SRDC, Fishkill, NY
Mentor/Manager : Paul Parries chief technologist ; Toshiaki Kirihata Manager
High-performance, highly reliable eDRAM design using 45nm SOI technology
Body history study on 12s eDRAM sensing scheme for P7 macro and ASIC macro
Defect modeling and comprehensive analysis of its impact on sensing margin
Optimization of sensing scheme in the presence of process variations and defects for p7 macro
Established in the eDRAM design team the best practice to evaluate floating body/body history effect

Circuit Design Tools : HSPICE, Powerspice, Spectre, Cadence IC design tools for schematic and layout
Hardware Development Language : Verilog, VHDL
Software Languages and Scripts : C++, PERL
Device and Process Simulators : MEDICI, TAURUS, Tsuprem4, HFSS
Mathematical Software : MATLAB
Operating Systems : Windows, UNIX, AIX
VLSI Nanofabrication Process and Characterization : wetbenches, optical lithography, wet etching, metal deposition, probe station

Digital CMOS design Advanced VLSI design Reliability Physics Of Semiconductor Devices Integrated Circuits Fabrication Lab Analog IC design Distributed Parameter System RF design Digital Signal Processing Advanced VLSI device Random Variables and Probability Quantum Transport Phenomena Solid State Physics-I and II Communication Theory

August, 2004 -  Present
Professor

Heterogeneous 3 - D system using low cost flexible electronics for improved reliability
Highly reliable, low cost, reconfigurable and hybrid 3 - D electronic system using Low Temperature Poly-Si Thin-Film Transistors LTPS TFTs
Physics-based and SPICE compatible models considering carrier transport at Si grain and thermionic emission across the grain boundary GB regions
Device modeling and simulation
Electrical characterization and SPICE-comparable modeling
Developed a device optimization methodology for LTPS TFTs
A novel scaling rule under low thermal budget from design perspective
Process optimization methodology from manufacturing perspective
Developed a statistical simulation methodology based on material properties to estimate the inherent material variations on circuit performance
Modeling of intrinsic process variations due to material properties
Developed a statistical static timing analysis tool for estimation of circuit delay variability
Proposed design strategies for reducing variability in LTPS TFTs to improve the circuit robustness
Developed an efficient circuit design technique to alleviate the impact of process variation
Proposed a low cost, generic and fully reconfigurable hybrid 3 - D integrated system using LTPS TFTs for off-line, on-line test and verification of underlying complex VLSI systems
Proposed various design options for test structure using LTPS TFTs
Evaluation of test structures in terms of power/delay by designing various design-for-test/BIST components
Designed a generic and reconfigurable 3 - D test architecture over the chip to reduce the test overhead
Heterogeneous embedded memory system
High-performance, low-power and fault tolerant Spin Torque Transfer Magnetic RAM STT MRAM design using spintronics in collaboration with Prof.Sayeef Salahuddin UC, Berkeley.
Physics-based and SPICE compatible models for describing the coupled electro/magnetic dynamics of spintronic device and capturing its hysteresis nature for circuit simulation
A comprehensive analysis of failures in STT MRAM and device/circuit/architecture bottom-up design approach for reducing failures
Estimation model of failure probabilities and statistical circuit design technique for reducing failures. A key observation is the conflicting design requirements between memory stability and integration density
Developed various fault-tolerant cell design techniques to relax/decouple the conflicting design requirements
Proposed an alternative hierarchical design methodology circuit/architecture co-design. An emphasis on co-design approach takes advantage of the unique feature of spintronic device and makes both circuit and architecture design strongly correlated decoupled the conflicting design requirements
Both yield and density are improved with negligible performance penalty
High-performance, low-power and fault tolerant embedded DRAM eDRAM design using SOI and deep trench DT technology still in progress
Developed a comprehensive model to capture the dynamic behavior of micro sense amplifier SA during read and write operations predict the read stability and writability of a novel sensing scheme SA and power/performance
Capable of describing the statistics feature of SA in the presence of process variations, global and local parametric variations and temporal variation due to floating body and body history effects is validated by simulation and calibrated by hardware measurement
Will optimize design parameters of SA and array cell to reduce the memory failure probabilities due to process variation for yield enhancement

Lecture Teaching Assistant for ECE 453 Quantum Phenomena from Atom to transistor, 2005 - 2006.

2005 -  2006
Teaching Assistant

Instructor for ECE 306 Circuit and system design, 2006 - 2007.

Journal Papers published
Jing Li, K. Kang and Kaushik Roy ; Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low Power, Low-Cost Applications, IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems TCAD, vol. 28, no .1, pp. 46 - 59, January, 2009.
Jing Li, A. Bansal, S. Ghosh and Kaushik Roy, An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs, ACM Journal on Emerging Technologies in Computing Systems, vol .4, issue 3, pp13.1 13.19, August, 2008.
Jing Li, A. Bansal and Kaushik Roy ; Poly-Si Thin Film Transistors : An efficient and low cost option for digital sub-threshold operation, IEEE Transactions on Electron Devices TED, vol. 54, no. 11, pp 2918 - 2929, November, 2007.
Journal Papers under review
Jing Li, P. Ndai, A. Goel, S. Salahuddin and Kaushik Roy, Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM STT MRAM from Circuit/Architecture Perspective, submit to IEEE Transaction on VLSI Systems TVLSI, under review.
Conference Papers published
Jing Li, P. Ndai, A. Goel, H. Liu and Kaushik Roy, An Alternate Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM STT MRAM from Circuit/Architecture Perspective, accepted by Asia and South Pacific Design Automation Conf. ASP-DAC, 2008
Jing Li and Kaushik Roy, Modeling of Failure Probability and Statistical Design of Spin-Torque Transfer Magnetic RAM STT MRAM Array for Yield Enhancement, Technology and Talent for the 21st Century Technology TECHCON, SRC, 2008
Jing Li, H. Liu, S. Salahuddin and Kaushik Roy, Variation-Tolerant Spin-Torque Transfer STT MRAM Array for Yield Enhancement, Custom Integrated Circuits Conf. CICC, 2008
Jing Li, C. Augustine, S. Salahuddin and Kaushik Roy, Modeling of Failure Probability and Statistical Design of Spin-Torque Transfer Magnetic Random Access Memory STT MRAM Array for Yield Enhancement, Design Automation Conf. DAC, 2008.
Jing Li, S. Ghosh and Kaushik Roy, A generic and reconfigurable test paradigm using low-cost integrated Polysilicon TFTs, Intl. Test Conf. ITC, 2007.
Yiran Chen, H. Li, Jing Li and Cheng-Kok Koh, Variable-latency Adder VL-Adder : New Arithmetic Circuit Design Practice to Overcome NBTI, Intl. Symp. on Low Power Electronic Design ISLPED, 2007.
Jing Li and Kaushik Roy, Low Power and Variation Tolerant Digital Circuit Design in Sub-micron Regime using Low Cost LTPS TFTs, Technology and Talent for the 21st Century Technology TECHCON, SRC, 2007
Jing Li, K. Kang and Kaushik Roy, Novel variation-aware circuit design of scaled LTPS TFT for ultra low power, low-cost applications, Intl. Conf. on IC Design and Technology ICICDT, 2007
Jing Li, K. Kang, A. Bansal and Kaushik Roy, High performance and low power electronics on flexible substrates, Design Automation Conf. DAC, 2007.
Jing Li, A. Bansal and Kaushik Roy ; Exploring low temperature Poly-Si for low cost and low power sub-micron digital operation, Device Research Conf. DRC, 2006.
Technical Report
Jing Li, Body History Study on 12s eDRAM Sensing Operation, Semiconductor Research and Development Center, Fishkill, IBM, 2008
PATENT Jing Li, S. Ghosh and Kaushik Roy, Generic and reconfigurable test paradigm using low-cost integrated Polysilicon TFTs, patent filed with Purdue Research Foundation with support from DARPA.
INVITED TALKS Robust Design in Emerging Technologies, Intel Corporation, 2 : 00 pm-3 : 30 pm PDT, 2/1/2008.
A Genetic and Reconfigurable Test Paradigm Using Low-Cost Integrated Poly-Si TFT, LSI Corporation, 1 : 30 pm-3 : 30 pm PDT, 10/19/2007.
PRESENTATIONS Modeling of Failure Probability and Statistical Design of Spin-Torque Transfer Magnetic RAM STT MRAM Array for Yield Enhancement, at Technology and Talent for the 21st Century Technology TECHCON, SRC, Austin, TX, November 2008.
Body History Study on 12s eDRAM Sensing Operation, Semiconductor Research and Development Center, Fishkill, IBM, 2008.
Modeling of Failure Probability and Statistical Design of Spin-Torque Transfer Magnetic Random Access Memory STT MRAM Array for Yield Enhancement, at Design Automation Conference DAC, Anaheim, CA, June 2008.
A generic and reconfigurable test paradigm using low-cost integrated Polysilicon TFTs, at Intl. Test Conf. ITC, Santa Clara, October 2007.
Low Power and Variation Tolerant Digital Circuit Design in Sub-micron Regime using Low Cost LTPS TFTs, at Technology and Talent for the 21st Century Technology TECHCON, SRC, Austin, TX, September 2007.
Novel variation-aware circuit design of scaled LTPS TFT for ultra low power, low-cost applications, at Intl. Conf. on IC Design and Technology ICICDT, Austin, TX, June 2007.
High performance and low power electronics on flexible substrates, at Design Automation Conf. DAC, San_Diego, CA, June 2007.

Reviewer of Electronic Device Letters IEEE EDL.

2007 -  2008

2007 -  2008

Presented a poster in C2S2 annual review, 2008.
Presented a poster in GSRC annual review, 2009.

Education

Publications

MEMBERSIP OF
Professional associations Student member of Gigascale Systems Research Center GSRC .
Student member of Focus Center Research Program FCRP .
Student member of Nanoelectronics Research Initiative NRI .
Student member of Semiconductor Research Corporation SRC .
Student member of IEEE .
Student member of ACM SIGDA .
Member of society of women engineers SWE .


Miscellaneous

Shanghai Jiao Tong University, Shanghai, China with honors