Objective


To obtain a position as an Analog, Mixed Signal RF BiCMOS Layout Designer



Summary



I am an Analog/Mixed Signal Layout Designer, who tries to do better in layout design with higher yield and the execution of large and deadline sensitive IC layout work.



Employment

January, 2009 -  May, 2009
RF Mixed Signal Layout Designer

Analog RF layouts and full custom digital layouts.
Bandgap, VBK_SW, LDO, RC_OSC, ISLAND0, ESD structures
Cells and Blocks level floor planning.
UMC 90 Nano RF process
Implementation of high frequency layouts, DFM, WPE, ABBA, CC matching, parasitic matching and high yield layouts.
Used Cadence VXL, Calibre for DRC and LVS verifications.

December, 2008 -  January, 2009
RF Analog Layout Designer

Analog RF layouts and full custom digital layouts.
Regulator Layout and cells and blocks level layouts.
TSMC 130 Nanometer RF process
Implementation of high frequency layout, DFM, WPE, ABBA, CC matching and parasitic matching and high yield layouts.
Used Cadence VXL, Calibre for DRC and LVS verifications.

November, 2008 -  December, 2008
RF Analog Layout Designer

Analog RF layout and full custom digital layout
Charge Pump Layout, Cells and Blocks level layouts.
TSMC 90 Nanometer RF process
Implementation of high frequency layout, DFM, WPE, ABBA, CC matching and parasitic matching and high yield layouts.
Used Cadence VXL, Calibre DRC and LVS verifications.

August, 2008 -  November, 2008
Analog Layout Designer

Analog or Mixed Signal full custom digital layouts, cells, blocks level and power mash.
Regulator18v_fend, Regulator18v_Syn2 adcbuffer_offse_mux
Cmfb_high1_satd4, Irefabsnux7ls_v1, Registers_top
Used NEC 55 Nanometer process
Implementation of high frequency layout, DFM, WPE, ABBA, CC matching and parasitic matching and high yield layouts.
Used Cadence VXL, Laker, Calibre LVS and Calibre DRC verifications.

April, 2008 -  July, 2008
Mixed Signal RF IC Layout Designer

RFIC
Ultra wide band, High frequency custom layout.

PLL and ADC and others, Blocks level floor planning.
Used TSMC 65 nanometer process.
Implementation of high frequency layout, DFM, WPE, ABBA, CC matching and parasitic matching and high yield layouts.
Used Cadence VXL, Assura and Calibre for DRC and LVS verifications.

June, 2007 -  March, 2008
Mixed Signal Layout Designer

Implemented High Speed full customer Mixed Signal layouts.
Responsible for implementation of cells, block level and top level assembly.
Implementation of the methodology, power grids and the floor planning.
Helped layout PLL, Fast Channel Receiver, DCI receiver, Equalizer, Amplifier
ESD Devices, Cells and Blocks level layout.
Used TSMC 65 nanometer process, Used Cadence Virtuoso XL, Assura, Calibre for DRC and LVS.

January, 2006 -  April, 2007
Mixed Signal Layout Designer

Mixed Signal Analog and Digital layouts, full custom sensing IC layouts.
Responsible for the layout of Sensor Driver, ADC, Analog Control Registers, Servo Gain Controller, Master bias, SRAM, IO Pad Ring, blocks levels cells and the chip level floor planning and placement for the 1 touch sensing chip and the test chips.
Responsible for Power, Ground routing, signal routing, floor planning and debugging.
Used Cadence VXL, auto routing tools and Assura for DRC and LVS.

January, 2005 -  January, 2006
Mixed Signal RF Layout Designer

High speed, BICMOS, Analog and Digital, full custom layouts.
Responsible to layout Power Detectors-80MHz to 900 MHz, 1.2 GHz band pass filter using passive inductors with active negative resistors for loops compensation, 1.2 GHz low noise amplifier, high frequency mixers and Bondpad designs with Z5D structures
Used Cadence VXL, Assura for DRC and LVS verifications.
Used IBM 5HPE process. 35um SiGE Bicmos

January, 2004 -  January, 2005
Mixed Signal Layout Designer

High - speed CMOS, Analog and Digital, full custom Image Sensor layouts.
Responsible to layout Bandgap, Bandgap-buf, Video DAC, Opamps, Column Driver, Row Driver, ADC, IO Padring, PLL and Chip level layout.
Used Cadence Virtuoso, Assura, Calibre for DRC and LVS verifications.

October, 2003 -  January, 2004
Mixed Signal Layout Designer

High - speed CMOS, Bipolar, Analog and Digital, full custom LCOS Microdisplay and Aasic Chip layout.
Responsible to layout Pixel, Bandgap, Bandgap-buf, Video DAC, Opamps, Iref, 8bit Full scale adjust, Dac8_diff_full, Column Driver, Row Driver, Amux, IDAC 10 bit source and Level Shifter, Floor planning and Chip level.
Used Cadence VXL, Assura and Draula for DRC and LVS.
Used Hynix, TSMC, Magnachip, Fujitsu and UMC process.

January, 2003 -  October, 2003
Mixed Signal RFLayout Designer

High - speed CMOS, Bipolar, Analog and Digital, full custom RFIC layouts.

Responsible to layout PLL, Amplifiers, Oscillators, Mixers, Synthesizer, LNA, VCO and others cells and blocks level planning.
Used Cadence VXL, Assura, Diva verifications tools for DRC, LVS.
Used IBM Process.

November, 2002 -  January, 2003
Mixed Signal Layout Designer

High Speed CMOS, Digital, full custom layout.
Responsible for layout cells to blocks level layout and top level floor planning.
Used Cadence VXL. Dracula, Calibre for DRC, ERC and LVS.
Used TSMC and UMC process.

March, 1999 -  November, 2002
Mixed Signal Layout Designer

CMOS, BICMOS,
Analog and Digital, full custom layout.
Responsible to layout cell level, block level and top level floor planning.
Used Cadence Virtuoso layout editor, DIVA, Dracula for DRC, LVS and ERC.
Helped layout amplifiers, MLT3 line driver, PLL, Synthesizer.

Clock recover and other complex layout for Mixed Signal 10/100 Base T and 10Gbps. Used TSMC and Atmel process.

1978 -  1998
CAD Designer

Education

Miscellaneous

Designed and Drafting services for Power and Pipeline Projects.
Mechanical Engineering and Technical Illustrations.